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cy7c1041bn 256 k 16 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06496 rev. *g revised september 4, 2013 256 k 16 static ram features temperature range: ? commercial: 0 c to 70 c ? automotive-a: ?40 c to 85 c high speed ? t aa = 15 ns low active power ? 1540 mw (max.) low cmos standby power ? 2.75 mw (max.) 2.0 v data retention (400 ? w at 2.0 v retention) automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free and non pb-free 44-pin tsop ii and molded 44-pin (400-mil) soj packages functional description the cy7c1041bn is a high-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041bn is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout. 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256 k x 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce we ble bhe logic block diagram
cy7c1041bn document number: 001-06496 rev. *g page 2 of 15 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc? solutions ...................................................... 15 cypress developer community ................................. 15 technical support ................. .................................... 15
cy7c1041bn document number: 001-06496 rev. *g page 3 of 15 pin configurations selection guide description -15 -20 unit maximum access time 15 20 ns maximum operating current commercial 190 170 ma automotive-a ? 190 ? maximum cmos standby current commercial 0.5 0.5 ma automotive-a ? 6 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc tsop ii
cy7c1041bn document number: 001-06496 rev. *g page 4 of 15 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v cc to relative gnd [1] .................................?0.5 v to +7.0 v dc voltage applied to outputs in high z state [1] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [1] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 5 v 0.5 automotive-a ?40 c to +85 c electrical characteristics over the operating range parameter description test conditions -15 -20 unit min max min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 ? 0.4 v v ih [1] input high voltage ? 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il [1] input low voltage ? ?0.5 0.8 ?0.5 0.8 v i ix input load current gnd < v in < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current max v cc , f = f max = 1/t rc commercial ? 190 ? 170 ma automotive-a ? ? ? 190 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?40?40ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 commercial ? 0.5 ? 0.5 ma automotive-a???6ma notes 1. v il (min.) = ?2.0 v for pulse durations of less than 20 ns. 2. t a is the case temperature.
cy7c1041bn document number: 001-06496 rev. *g page 5 of 15 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 8 pf c out i/o capacitance 8pf ac test loads and waveforms figure 1. ac test loads and waveforms data retention characteristics over the operating range (commercial only) parameter description conditions [4] min max unit v dr v cc for data retention ? 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?200 ? a t cdr [5] chip deselect to data retention time 0?ns t r [6] operation recovery time t rc ?ns data retention waveform figure 2. data retention waveform 90% 10% 3.0 v gnd 90% 10% all input pulses 5 v output 30 pf including jig and scope 5 v output 5 pf including jig and scope (a) (b) ?? 3 ns ? 3 ns output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 equivalent to: venin equivalent 1.73 v th ? 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc notes 3. tested initially and after any design or proce ss changes that may affect these parameters. 4. no input may exceed v cc + 0.5 v. 5. tested initially and after any design or proce ss changes that may affect these parameters. 6. t r < 3 ns for the ?15 speed. t r < 5 ns for the -20 and slower speeds.
cy7c1041bn document number: 001-06496 rev. *g page 6 of 15 switching characteristics over the operating range parameter [7] description -15 -20 unit min max min max read cycle t power v cc (typical) to the first access [8] 1?1? ? s t rc read cycle time 15 ? 20 ? ns t aa address to data valid ? 15 ? 20 ns t oha data hold from address change 3 ? 3? ns t ace ce low to data valid ? 15 ? 20 ns t doe oe low to data valid ? 7 ? 8 ns t lzoe oe low to low z 0 ? 0? ns t hzoe oe high to high z [9, 10] ?7 ? 8 ns t lzce ce low to low z [10] 3? 3? ns t hzce ce high to high z [9, 10] ?7 ? 8 ns t pu ce low to power-up 0 ? 0? ns t pd ce high to power-down ? 15 ? 20 ns t dbe byte enable to data valid ? 7?8 ns t lzbe byte enable to low z 0?0? ns t hzbe byte disable to high z ? 7?8 ns write cycle [11, 12] t wc write cycle time 15 ? 20 ? ns t sce ce low to write end 12 ? 13 ? ns t aw address setup to write end 12 ? 13 ? ns t ha address hold from write end 0 ? 0? ns t sa address setup to write start 0 ? 0? ns t pwe we pulse width 12 ? 13 ? ns t sd data setup to write end 8 ? 9? ns t hd data hold from write end 0 ? 0? ns t lzwe we high to low z [13] 3? 3? ns t hzwe we low to high z [13, 14] ?7? 8 ns t bw byte enable to end of write 12 ? 13 ? ns notes 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 8. this part has a voltage regulator which steps down the voltage from 5 v to 3.3 v internally. t power time has to be provided initially before a read/write operation is started. 9. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage. 10. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 11. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 12. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage.
cy7c1041bn document number: 001-06496 rev. *g page 7 of 15 switching waveforms figure 3. read cycle no. 1 [15, 16] figure 4. read cycle no. 2 (oe controlled) [16, 17] previous data data out valid t rc t aa t oha address data i/o valid 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data i/o v cc supply t dbe t lzbe t hzce bhe , ble current notes 15. device is contin uously selected. oe , ce , bhe , and/or bhe = v il . 16. we is high for read cycle. 17. address valid prior to or coincident with ce transition low.
cy7c1041bn document number: 001-06496 rev. *g page 8 of 15 figure 5. write cycle no. 1 (ce controlled) [18, 19] figure 6. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t data in valid t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce data in valid notes 18. data i/o is high impedance if oe or bhe and/or ble = v ih . 19. if ce goes high simultaneously with we going high, the output remains in a high-impedance state.
cy7c1041bn document number: 001-06496 rev. *g page 9 of 15 figure 7. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe data in valid
cy7c1041bn document number: 001-06496 rev. *g page 10 of 15 truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc )
cy7c1041bn document number: 001-06496 rev. *g page 11 of 15 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. speed (ns) ordering code package name package type operating range 15 cy7c1041bnl-15zxc 51-85087 44-pin tsop type ii (pb-free) commercial 20 cy7c1041bn-20zsxa 44-pin tsop type ii automotive-a cy 7 c 1 - 04 1 data width x 16-bits 4-mbit density fast asynchronous sram family technology code: c = cmos sram company code: cy = cypress bn 180 nm technology l low power xx speed: xx = 15 ns / 20 ns zx / zsx zx / zsx = 44-pin tsop ii (pb-free) x temperature range: c = commercial; a = automotive-a
cy7c1041bn document number: 001-06496 rev. *g page 12 of 15 package diagrams figure 8. 44-pin tsop z44-ii package outline, 51-85087 51-85087 *e
cy7c1041bn document number: 001-06496 rev. *g page 13 of 15 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius vvolt mhz megahertz a microampere ma milliampere mv millivolt mw milliwatt ns nanosecond pf picofarad wwatt
cy7c1041bn document number: 001-06496 rev. *g page 14 of 15 document history page document title: cy7c1041bn, 256 k 16 static ram document number: 001-06496 revision ecn orig. of change submission date description of change ** 424111 nxr see ecn new data sheet. *a 498575 nxr see ecn added automotive-a operating range updated ordering information table *b 2897061 aju 03/22/10 removed obsolete pa rts from ordering information table updated package diagrams *c 2906679 nxr 04/07/10 removed inactive part cy 7c1041bnl-20vxct from the ordering information table. *d 3086674 pras 11/15/10 removed inactive parts (cy7c1041bn-15zxi, cy7c1041bn-15vxi). added ordering code definition. *e 3232637 pras 04/20/2011 fixed unit for input load curr ent and output leakage current under electrical characteristics table from ma to a. updated template. added units table. *f 3383869 tava 09/26/2011 removed all refe rences to industrial information. all ?commercial-l? changed to ?commercial?. modified the notes in figures under read cycle and write cycle sections. rearranged sections for better clarity. revised package diagram. *g 4113666 vini 09/04/2013 updated package diagrams : spec 51-85087 ? changed revision from *d to *e. updated in new template. completing sunset review.
document number: 001-06496 rev. *g re vised september 4, 2013 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1041bn ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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